1. Technical Field
The present disclosure relates to a semiconductor electronic device provided with an integrated galvanic isolator element, in particular for the insulated transfer of data and/or power signals between two electronic integrated circuits, and to a related assembly process.
2. Description of the Related Art
As is known, many electronic applications transfer signals, which convey some sort of information, or electric power or energy, between two distinct electrical/electronic circuits, without any electrical connection by metal conductors between the same circuits (i.e., without a passage of electrical current occurring through an ohmic connection path). In other words, such applications include two distinct electronic circuits that communicate without contact, being “galvanically” insulated from one another.
For example, a galvanic insulation is commonly used in medical apparatuses (for example, for protecting users from electrical discharge), in applications for industrial automation (for example, for separating the parts operating at high voltage/power from the control parts, or for preventing destructive “ground loops” in the case of interconnections with different ground potentials), or in automotive applications (for example, in the production of electric engines for hybrid vehicles), or in consumer electronics (for example in the production of insulated AC/DC or DC/DC converters).
One of the two electronic circuits, and in particular the corresponding conductive portions at the reference potential, can be at a potential even markedly different from the corresponding portions of the second electronic circuit. This potential difference may also be variable, thus preventing the possibility of using a single common conductor with respect to which the signals are referenced. Finally, there are applications that guarantee an insulation between two electronic circuits (even for voltages of up to some kilovolts), which cannot be achieved with “level shifter” type solutions, in so far as a complete insulation would not be achieved and providing semiconductor components with operating voltages that are so high would become difficult and costly.
Numerous solutions have been proposed for obtaining galvanic isolators in integrated technology (i.e., by using the manufacturing techniques of the semiconductor industry or, in general, of microelectronics). Generally, integrated galvanic isolators are currently divided into three main classes, according to the operating principle adopted.
A first class includes optical couplers, which envisage transmission of signals by using light radiation through a medium transparent thereto, and in particular using a LED-phototransistor pair for carrying out a double electro-optical conversion, in transmission and reception. The main problems linked to this class of isolators are due to the low efficiency of the manufacturing process and to the limited data transfer rate (the so-called “bit rate”) that can be achieved, given by the signal conversion, mentioned above, from the optical domain to the electrical domain, and vice versa. In addition, it is known that generally the performance of optical couplers are bound to undergo degradation over time.
Belonging to a second class are capacitive-coupling isolators, in which the galvanic insulation is guaranteed by the presence of an appropriate dielectric set between two conductors (which provide the plates of a capacitor). Capacitive-coupling isolators, albeit enabling high transfer rates to be achieved, are limited by a reduced immunity to voltage transients (the so-called dV/dt), which occur for example when the difference of potential between the two electronic circuits to be insulated varies suddenly; these transients cause generation of high currents that are potentially destructive. Furthermore, this type of isolators does not enable transfer of the d.c. content of the signals, and in particular does not enable transfer of electric power.
The third class includes isolators, envisaging the use of variable magnetic fields for the transfer of signals, and in particular use of a coupling of an inductive, or magnetic, type.
Belonging in this class are, for example, isolators based upon the giant-magnetoresistive (GMR) effect. In these isolators, a first circuit implements a coil driven by a generator, the current of which represents the signal to be transferred (for example, by appropriate modulations), for generating a variable magnetic field. The magnetic field modulates the resistance of magnetoresistive sensors in a second circuit, which is to be insulated with respect to the first. The resistance variation of the magnetoresistive sensors, appropriately arranged in a bridge circuit configuration, produces a voltage that reproduces the transmitted signal. The galvanic insulation is ensured by the insulating material that physically separates the two circuits.
Other isolators, based upon inductive coupling, use a transformer for carrying out insulated transmission of signals between a first electronic circuit and a second electronic circuit. In general, these isolators envisage the use of two coils of conductive material, for example metal, set in the proximity of one another and separated by an appropriate dielectric medium; the coils provide the primary and secondary windings of a transformer, for the insulated transfer of data and/or power signals.
Advantageously, given that it is an intrinsically symmetrical system, a transformer can be operated in reverse to transfer information from the secondary winding to the primary winding, thus enabling provision of a bi-directional system. Furthermore, galvanic isolators based upon inductive coupling enable high transfer rates to be obtained, maintaining a high insensitivity to common-mode transients.
Various solutions have so far been proposed for integrated implementation of transformers for galvanic insulation.
For example, U.S. Pat. No. 7,064,442 and US 2008/0179963 disclose respective electronic devices, comprising in general, and as illustrated schematically in FIG. 1: a first electronic integrated circuit (IC) 2 and a second electronic integrated circuit (IC) 3 (operating, respectively, as “transmitter” and “receiver” of the signals to be transferred), integrating respective electronic components, provided respectively in a first die 4 and in a second die 5 of semiconductor material; and moreover a transformer 6, entirely integrated in a third die 7, which is also made of semiconductor material, for example silicon and set between the dice 4, 5 of the first and second electronic integrated circuits 2, 3, so as to provide the galvanic insulation required between the circuits. The first, second, and third dice 4, 5, 7 are assembled within one and the same package, designated as a whole by 8, and appropriate electrical-connection structures 9 are provided, for example with wire-bonding techniques (i.e., with the use of connection wires), between a primary winding 6a of the transformer 6 and the first electronic integrated circuit 2, and between a secondary winding 6b of the same transformer 6 and the second electronic integrated circuit 3.
The transformer 6 can be formed in the corresponding third die 7, with a “vertical” process, that is, the primary 6a and secondary 6b windings are separated vertically by an appropriate dielectric layer; or with a “horizontal” process, that is, the conductive portions defining both the primary winding 6a and the secondary winding 6b are provided a same surface of a dielectric layer. The latter solution can be, however, disadvantageous in so far as the insulation between the primary winding and the secondary winding of the transformer must be in this case guaranteed not only through the thickness of the dielectric layer, but also on the surface of the same dielectric layer.
In general, the aforesaid solution for providing the galvanic-insulation transformer has some drawbacks linked to the need of envisaging complex electrical-connection structures 9 for the electrical connection of the various distinct parts of which the corresponding electronic devices are made up, and moreover linked to the occupation of area within the package.
A further solution of a known type for providing a transformer as galvanic isolator envisages the use of just two dice of semiconductor material, as schematically illustrated in FIG. 2.
In particular, in a first die, once again designated by 4, the first electronic integrated circuit 2 is provided, for example operating as a transmitter of the signals to be transferred. Instead, both the second electronic integrated circuit 3, having functions of receiver, and the transformer 6, designed to provide the galvanic insulation between the first electronic integrated circuit 2 and the second electronic integrated circuit 3, are provided in a second die 5, set so as to be physically distinct and insulated from the first, but for appropriate electrical connections (for example, provided with the wire-bonding technique). The first and second dice 4, 5 are conveniently assembled within a single package.
In greater detail, the second electronic integrated circuit 3 (shown schematically in FIG. 2 as comprising a plurality of doped regions 3a) is provided with standard processing techniques (for example of a CMOS type, referred to as “baseline CMOS processing”, or of a DMOS type) in a structural layer 10 of the second die 5. A passivation layer 11, of dielectric material, is formed on the structural layer 10; within this passivation layer, various metal levels are provided, of which FIG. 2 shows by way of example only a bottom metal level 12 (set in the proximity of the structural layer 10), and a top metal level 13 (set at a distance from the same structural layer 10).
The metal levels, appropriately connected vertically to one another, provide electrical connections towards the second electronic integrated circuit 3. Furthermore, portions of the top metal level 13, appropriately shaped like a coil, provide the secondary winding 6b of the transformer 6.
An insulating layer 14, made of dielectric material, for example polyamide, having a given thickness, is provided on the top metal level 13 and the passivation layer 11; the primary winding 6a of the transformer 6 is provided on the outer surface of the insulating layer 14 (not in contact with the underlying layers), set vertically in a position corresponding to the secondary winding 6b, for example formed with techniques of deposition of a conductive layer (such as, for example, gold). The primary winding 6a is electrically connected to the first electronic integrated circuit 2 in the first die 4, by means of electrical-connection structures 9, for example including connection wires.
The aforesaid insulating layer 14 is deposited on the passivation layer 11, for example by deposition from liquid precursor. In addition, the insulating layer 14 is appropriately removed at the electrical contacts towards the second electronic integrated circuit 3 so as to enable electrical connection thereof towards the outside world by means of appropriate connection elements 15 (for example, once again with the wire-bonding technique).
Although presenting some specific advantages, for example in terms of a reduction of the overall dimensions and of the complexity of the electrical connections, this solution is not free from disadvantages either, some of which afflict in general the known embodiments proposed so far.
In particular, manufacturing of the transformer 6 requires appropriate post-processing steps, which are carried out on top of the structural layer 10 in which, in this case, the second electronic integrated circuit 3 has already been formed. This post-processing may consequently damage the underlying integrated circuit, for example on account of the thermal cycles associated thereto, and in general entails an increase in the complexity and manufacturing costs of the resulting electronic devices.
Furthermore, the characteristics of galvanic insulation of the transformer 6 are linked in this case to the intrinsic and geometrical characteristics of the insulating layer 14, physically set between the primary and secondary windings 6a, 6b of the transformer 6.
However, the post-processing techniques enable thicknesses of insulating material to be achieved that are not greater than a given threshold (for example, having a typical value not greater than 20 μm), thus representing a very precise limit for the maximum insulation voltage that can be achieved.
A further solution for providing a galvanic insulation between two integrated circuits of an electronic device, proposed by the present applicant and described, for example, in EP-A-1 990 914, envisages use of appropriate modulation/demodulation techniques for transmitting a radio-frequency signal from a first micro-antenna set on a first integrated circuit to a second micro-antenna positioned on a second integrated circuit. The two integrated circuits, and the respective micro-antennas, are provided in respective dice of semiconductor material, which can be arranged on one another within one and the same package in such a way as to enable communication between the micro-antennas.
This solution enables high transfer rates to be achieved, with reduced costs and manufacturing complexity; however, the transferred signals may at times be weak on account of the losses induced by the substrates of the aforesaid dice that are set between the micro-antennas. Furthermore, the modulation/demodulation techniques require the use of dedicated transmitter/receiver circuits, entailing an increase of the circuit complexity.
Another galvanic isolation arrangement is shown in US 2010/0265024 to Nakashiba. In Nakashiba, an interconnect substrate, on which a second inductor of a transformer is made, is attached on both of first and second dice by solder balls (having a diameter of around 20 μm). This arrangement involves technical difficulties and limitations that make it unsuitable for production on an industrial level.
First, the distance laterally separating the two dice determines the electrical insulation between the two dice, and therefore is a parameter that must be controlled closely. A first limitation is that this distance cannot be high (contrary to what would be desired for the electrical insulation), to avoid unnecessary increasing the lateral size of the interconnect substrate (and all connections carried by the same substrate). Therefore, placing the interconnect substrate on the two dice requires simultaneous accurate control of all these parameters:
distance between the dice;
alignment between the electrical contacts between the interconnect substrate and the first die; and
alignment between the electrical contacts between the interconnect substrate and the second die.
Since alignment of dice is independent of the subsequent placement of interconnect substrate, a maximum tolerance of 14 μm is allowed during manufacturing (considering a diameter of 20 μm for the solder balls). This level of precision is extremely difficult at the industrial level.
Moreover, when the first and second dice are placed on respective lead frames, the distance between the frames will be similar to the distance between the dice, with possible problems of electrical insulation between the frames.
In Nakashiba, also the vertical alignment between the two dice (in particular between the respective front surfaces) is also a source of problems, since it may lead to inclination of the interconnect substrate due to the different thicknesses of the first and second dice (the thickness of a die cannot be typically controlled with repeatability and precision lower than 10 μm), and also to the different thickness of the die attach materials.
A further point to consider is how the insulation between the inductors in the transformer is achieved in Nakashiba. In Nakashiba, the interconnect substrate is simply, as the name suggests, a connecting structure and does not influence the galvanic insulation properties. In Nakashiba, insulation is provided by the separation distance between the dice and by the thickness of the dielectric stack in the first die. Because of this, the first inductor in the first die has to be made in the lower metal layers, and this is per se not advantageous, since these metal layers are those with highest resistivity and low current density. Accordingly, this implies further difficulties in having transformers with high Q and efficiency.